In conventional photolithographic processing, features are created on an integrated circuit or other device by exposing a mask pattern onto a wafer that is coated with light sensitive resist materials. After exposure, the wafer is chemically and mechanically processed to create the features defined by the exposure pattern.
As the features created on a wafer become increasingly small, optical and other process distortions occur whereby the pattern of features that is desired to be created on a wafer will not match the pattern of features that is actually created on the wafer. To compensate for distortions, many photolithographic processes use one or more resolution enhancement techniques to improve the fidelity with which the desired pattern is printed on the wafer.
In most resolution enhancement techniques such as optical and process correction (OPC), a simulation is made of how a feature will print on a wafer. The simulation is then used to adjust a pattern contained on a mask or reticle in a way that compensates for the expected distortions. As part of the simulation, a model can be used that predicts how the light sensitive resist materials will behave when exposed with a particular mask pattern. Typically, simulations are conducted at sparsely chosen sampling locations or sites to reduce the overall processing time spent on simulation. The local values of image intensity and related other properties, such as derivatives, are calculated at these simulation sites to estimate the behavior of the resist at that point. Suitable site selection procedures are the subject of other inventions in this field, see for example U.S. Pat. No. 7,073,162, and U.S. Patent Publication No. 2005/0278686, both of which are herein incorporated by reference, to ensure the best representation when a sampling approach is taken.